The advantages of transmitting data and voice information in packets has long been recognized. Packet switching provides a known solution to problems where the information to be transmitted occurs in short, high-rate bursts, with long pauses between bursts.
As the number of different applications for packet switching grows, the requirements have become more stringent on packet switching systems. They must be capable of routing the packets to their destination, preferably through the use of an address contained within the packet itself. In addition, the system must provide buffering at different nodes within the system to allow for the temporary storage of packets if the intended route of those packets is temporarily experiencing traffic delays. Many of the emerging applications for packet switching, such as for the switching of digitally encoded voice information, require a packet switching system having thousands of the switching nodes. An important goal in the design of such large packet system is that each node be capable of rapidly switching packets and especially have a reasonable physical size.
Prior art systems for switching packets have been rather small systems consisting of only a few hundred nodes. In addition, such systems have employed large computers using sophisticated software packages to perform the packet switching functions at the nodes within the system. The systems customarily have used complex control protocols to handle the problems of error recovery and flow control and, as a result, have had a limited packet handling capability of only a few thousand packets per second.
Typically, in the prior art, when a packet was received, a computer examined the logical address to determine the destination of the packet and then executed the necessary steps to effect a transmission of the packet to that destination. The process involved the time consuming steps at each node of translating the logical address into a physical address of the transmission link over which the packet was to be retransmitted, and then, after receiving and buffering the entire packet, performing error and flow control functions followed by actual packet retransmission to a succeeding node. Obviously, such a complicated process results in substantial throughput switching delays and undesirably introduces variable delays at the different switching nodes which culminates in packets arriving out of sequence at their destination.
Not only are known prior art systems unable to implement a toll switching network function because of the undesirable switching delay, but the existing structures for switching node architectures heretofore would be physically too large if expanded to perform the toll function. The prior art architectures do not lend themselves well to physical reductions which are possible through the use of very large scale integration (VLSI).
In light of the foregoing, it is apparent that a need exists for a packet switching system which transmits packets with a minimal amount of delay and which has an architecture and protocol of operation for high capacity packet switching through packet switches of reasonable physical size.